A first-in-first-out circuit (sometimes referred to as a FIFO) is a buffer circuit often used in an integrated circuit for transferring data from one system domain to another. A FIFO has a first port at which input data can be received and a second port at which output data can be provided.
Data stored in the FIFO may be grouped into respective units sometimes referred to as data words. For example, consider a scenario in which the FIFO receives a first data word at a first point in time, a second data word at a second point in time after the first point in time, and a third data word at a third point in time after the second point in time. These data words are stored in the FIFO until they are read out. When reading out data from the FIFO, the first data word will be the first data to be presented at its output (because the first data word arrived at the FIFO prior to the second and third data words). The second and third data words can then be read out in that order.
A FIFO is typically implemented using an array of dual-port memory cells formed on an integrated circuit. The array of dual-port memory cells are arranged in rows and columns. Each dual-port memory cell along the same row is controlled using two corresponding address signals, whereas each dual-port memory cell along the same column is connected to two corresponding sense amplifiers. Each entry in the FIFO corresponds to a different group of dual-port memory elements in the array. Each dual-port memory cell has a write port and a read port. Operations performed using the read and write ports can be controlled using two independent clock signals (i.e., read and write requests for the FIFO can arrive asynchronously or synchronously).
Consider a scenario in which the conventional FIFO receives a read request and a write request synchronously and is configured to simultaneously write in a new data word and to read out an existing data word. If the FIFO is empty, only the write request will be serviced. If the FIFO is full, only the read request will be serviced. However if the FIFO is neither empty nor full, the write and read requests may be serviced in parallel. In this last scenario, if the group of cells to which the new data word is to be written and the group of cells from which the existing data word is to be read are located along the same address row, the dual-port memory performance may be substantially degraded. Performing simultaneous read and write accesses in this way may result in failed write operations, severely reduced read margins, and reduced die yield.